CNTFET四进制乘法器效率低于相应的二进制乘法器
摘要：N*N quaternary digit and 2N*2N bit CNTFET multipliers: a comparison of worst case delay, chip area, power, and power delay product for N=1, N=2, and N=4.
作者：Daniel Etiemble
论文ID：2206.03252
分类：Emerging Technologies
分类简称：cs.ET
提交时间：2022-06-08